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| PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Commercial/Express s Real-time and Programmed Wait State Bus Operation s Binary-code Compatible with MCS(R) 51 s Pin Compatible with 44-pin PLCC and 40pin PDIP MCS 51 Sockets s Register-based MCS(R) 251 Architecture -- 40-byte Register File -- Registers Accessible as Bytes, Words, or Double Words s Enriched MCS 51 Instruction Set -- 16-bit and 32-bit Arithmetic and Logic Instructions -- Compare and Conditional Jump Instructions -- Expanded Set of Move Instructions s Linear Addressing s 256-Kbyte Expanded External Code/Data Memory Space s ROM/OTPROM/EPROM Options: 16 Kbytes (SB/SQ), 8 Kbytes (SA/SP), or without ROM/OTPROM/EPROM s 16-bit Internal Code Fetch s 64-Kbyte Extended Stack Space s On-chip Data RAM Options: 1-Kbyte (SA/SB) or 512-Byte (SP/SQ) s 8-bit, 2-clock External Code Fetch in Page Mode s Fast MCS 251 Instruction Pipeline s User-selectable Configurations: -- External Wait States (0-3 wait states) -- Address Range & Memory Mapping -- Page Mode s 32 Programmable I/O Lines s Seven Maskable Interrupt Sources with Four Programmable Priority Levels s Three Flexible 16-bit Timer/counters s Hardware Watchdog Timer s Programmable Counter Array -- High-speed Output -- Compare/Capture Operation -- Pulse Width Modulator -- Watchdog Timer s Programmable Serial I/O Port -- Framing Error Detection -- Automatic Address Recognition s High-performance CHMOS Technology s Static Standby to 16-MHz Operation s Complete System Development Support -- Compatible with Existing Tools -- New MCS 251 Tools Available: Compiler, Assembler, Debugger, ICE s Package Options (PDIP, PLCC, and Ceramic DIP) A member of the Intel family of 8-bit MCS 251 microcontrollers, the 8XC251SA/SB/SP/SQ is binary-code compatible with MCS 51 microcontrollers and pin compatible with 40-pin PDIP and 44-pin PLCC MCS 51 microcontrollers. MCS 251 microcontrollers feature an enriched instruction set, linear addressing, and efficient C-language support. The 8XC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip RAM and is available with 8 Kbytes or 16 Kbytes of on-chip ROM/OTPROM/EPROM, or without ROM/OTPROM/EPROM. A variety of features can be selected by new user-programmable configurations. COPYRIGHT (c) INTEL CORPORATION, 1996 May 1996 Order Number: 272783-003 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. *Third-party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect IL 60056-764 or call 1-800-548-4725 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER System Bus and I/O Ports P0.7:0 P2.7:0 Code OTPROM/ROM 8 Kbytes or 16 Kbytes I/O Ports and Peripheral Signals P1.7:0 P3.7:0 Port 0 Drivers Port 2 Drivers Data RAM 512 Bytes or 1024 Bytes Port 1 Drivers Port 3 Drivers Memory Data (16) Memory Address (16) Watchdog Timer Bus Interface Code Bus (16) Code Address (24) Peripheral Interface Timer/ Counters Instruction Sequencer Data Address (24) Interrupt Handler IB Bus (8) PCA SRC2 (8) Data Bus (8) SRC1 (8) Serial I/O Clock & Reset Peripherals ALU Register File Data Memory Interface DST (16) MCS(R) 251 Microcontroller Core Clock & Reset 8XC251SA/SB/SP/SQ Microcontroller A4214-01 Figure 1. 8XC251SA/SB/SP/SQ Block Diagram PRELIMINARY 3 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 1.0 NOMENCLATURE X Te XX Pa ck 8 X o Pr X o Pr XXXXX o Pr XX v De Figure 2. The 8XC251SA/SB/SP/SQ Family Nomenclature Table 1. Description of Product Nomenclature Parameter Temperature and Burn-in Options Options no mark T Packaging Options N P C Program Memory Options 0 3 7 Process Information Product Family Device Memory Options C 251 SA SB SP SQ Device Speed 16 Description Commercial operating temperature range (0C to 70C) with Intel standard burn-in. Express operating temperature range (-40C to 85C) with Intel standard burn-in. 44-pin Plastic Leaded Chip Carrier (PLCC) 40-pin Plastic Dual In-line Package (PDIP) 40-pin Ceramic Dual In-line Package (Ceramic DIP) Without ROM/OTPROM/EPROM ROM User programmable OTPROM/EPROM CHMOS 8-bit control architecture 1-Kbyte RAM/8-Kbyte ROM/OTPROM/EPROM 1-Kbyte RAM/16-Kbyte ROM/OTPROM/EPROM or without ROM/OTPROM/EPROM 512-byte RAM/8-Kbyte ROM/OTPROM/EPROM 512-byte RAM/16-Kbyte ROM/OTPROM/EPROM or without ROM/OTPROM/EPROM External clock frequency mp gr ce du ic e ag ing Op tio ns am atu er ss In f ct m Fa e Sp -m a re nd em or ma tio yO ed ily or Bu rn -in n on pti s Op tio ns A2815-01 4 PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 2 lists the proliferation options. See Figure 2 for the 8XC251SA/SB/SP/SQ family nomenclature. . Table 2. Proliferation Options 8XC251SA/SB/SP/SQ (0 - 16 MHz; 5 V 10%) 80C251SB16 80C251SQ16 83C251SA16 83C251SB16 83C251SP16 83C251SQ16 87C251SA16 87C251SB16 87C251SP16 87C251SQ16 Table 3 lists the 8XC251SA/SB/SP/SQ packages. Table 3. Package Information Pkg. N P C TN TP Definition 44 ld. PLCC 40 ld. Plastic DIP 40 ld. Ceramic DIP 44 ld. PLCC 40 ld. Plastic DIP Temperature 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C CPU-only CPU-only ROM ROM ROM ROM OTPROM/EPROM OTPROM/EPROM OTPROM/EPROM OTPROM/EPROM PRELIMINARY 5 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 2.0 PINOUT P1.5 / CEX2 P1.6 / CEX3 / WAIT# P1.7 / CEX4 / A17 / WCLK RST P3.0 / RXD VCC2 P3.1 / TXD P3.2 / INT0# P3.3 / INT1# P3.4 / T0 P3.5 / T1 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 P1.4 / CEX1 P1.3 / CEX0 P1.2 / ECI P1.1 / T2EX P1.0 / T2 VSS1 VCC AD0 / P0.0 AD1 / P0.1 AD2 / P0.2 AD3 / P0.3 8XC251SA 8XC251SB 8XC251SP 8XC251SQ View of component as mounted on PC board 18 19 20 21 22 23 24 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 AD4 / P0.4 AD5 / P0.5 AD6 / P0.6 AD7 / P0.7 EA# / VPP VSS2 ALE / PROG# PSEN# A15 / P2.7 A14 / P2.6 A13 / P2.5 P3.6 / WR# P3.7 / RD# / A16 XTAL2 XTAL1 VSS VSS2 A8 / P2.0 A9 / P2.1 A10 / P2.2 A11 / P2.3 A12 / P2.4 A4205-02 Figure 3. 8XC251SA/SB/SP/SQ 44-pin PLCC Package 6 PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER P1.0 / T2 P1.1 / T2EX P1.2 / ECI P1.3 / CEX0 P1.4 / CEX1 P1.5 / CEX2 P1.6 / CEX3 / WAIT# P1.7 / CEX4 / A17 / WCLK RST P3.0 / RXD P3.1 / TXD P3.2 / INT0# P3.3 / INT1# P3.4 / T0 P3.5 / T1 P3.6 / WR# P3.7 / RD# / A16 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 VCC AD0 / P0.0 AD1 / P0.1 AD2 / P0.2 AD3 / P0.3 AD4 / P0.4 AD5 / P0.5 AD6 / P0.6 AD7 / P0.7 EA# / VPP ALE / PROG# PSEN# A15 / P2.7 A14 / P2.6 A13 / P2.5 A12 / P2.4 A11 / P2.3 A10 / P2.2 A9 / P2.1 A8 / P2.0 A4206-03 8XC251SA 8XC251SB 8XC251SP 8XC251SQ View of component as mounted on PC board 27 26 25 24 23 22 21 Figure 4. 8XC251SA/SB/SP/SQ 40-pin PDIP and Ceramic DIP Packages PRELIMINARY 7 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 4. 8XC251SA/SB/SP/SQ Pin Assignment PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 DIP VSS1 P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3/WAIT# P1.7/CEX4/A17/WCLK RST P3.0/RXD VCC2 P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 P3.6/WR# P3.7/RD#/A16 XTAL2 XTAL1 VSS Name PLCC 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 31 32 33 34 35 36 37 38 39 40 21 22 23 24 25 26 27 28 29 30 DIP VSS2 A8/P2.0 A9/P2.1 A10/P2.2 A11/P2.3 A12/P2.4 A13/P2.5 A14/P2.6 A15/P2.7 PSEN# ALE/PROG# VSS2 EA#/VPP AD7/P0.7 AD6/P0.6 AD5/P0.5 AD4/P0.4 AD3/P0.3 AD2/P0.2 AD1/P0.1 AD0/P0.0 VCC Name 8 PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 5. 8XC251SA/SB/SP/SQ PLCC/DIP Pin Assignments Arranged by Functional Category Address & Data Name AD0/P0.0 AD1/P0.1 AD2/P0.2 AD3/P0.3 AD4/P0.4 AD5/P0.5 AD6/P0.6 AD7/P0.7 A8/P2.0 A9/P2.1 A10/P2.2 A11/P2.3 A12/P2.4 A13/P2.5 A14/P2.6 A15/P2.7 P3.7/RD#/A16 P1.7/CEX4/A17/WCLK PLCC 43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 19 9 DIP 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 8 V CC V CC2 V SS V SS1 VSS2 Processor Control Name P3.2/INT0# P3.3/INT1# EA#/V PP RST XTAL1 XTAL2 PLCC 14 15 35 10 21 20 DIP 12 13 31 9 18 19 Bus Control & Status Name P3.6/WR# P3.7/RD#/A16 ALE/PROG# PSEN# PLCC 18 19 33 32 DIP 16 17 30 29 EA#/VPP Power & Ground Name PLCC 44 12 22 1 23, 34 35 31 20 DIP 40 P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3/WAIT# P1.7/CEX4/A17/WCLK P3.0/RXD P3.1/TXD P3.4/T0 P3.5/T1 Input/Output Name PLCC 2 3 4 5 6 7 8 9 11 13 16 17 DIP 1 2 3 4 5 6 7 8 10 11 14 15 PRELIMINARY 9 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 3.0 SIGNALS Table 6. Signal Descriptions Alternate Function P1.7/CEX4/ WCLK Signal Name A17 Type O Description 18th Address Bit (A17). Output to memory as 18th external address bit (A17) in extended bus applications, depending on the values of bits RD0 and RD1 in configuration byte UCONFIG0 (see Chapter 4, "Device Configuration," of the 8XC251SA/SB/SP/SQ Embedded Microcontroller User's Manual). See also RD# and PSEN#. Address Line 16. See RD#. Address Lines. Upper address lines for the external bus. Address/Data Lines. Multiplexed lower address lines and data lines for external memory. Address Latch Enable. ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A15:8 and AD7:0. An external latch can use ALE to demultiplex the address from the address/data bus. Programmable Counter Array (PCA) Input/Output Pins. These are input signals for the PCA capture mode and output signals for the PCA compare mode and PCA PWM mode. A16 A15:8 AD7:0 ALE O O I/O O RD# P2.7:0 P0.7:0 PROG# CEX4:0 I/O P1.6:3 P1.7/A17/ WAIT# EA# I External Access. Directs program memory accesses to on-chip or off- VPP chip code memory. For EA# = 0, all program memory accesses are offchip. For EA# = 1, an access is to on-chip ROM/OTPROM/EPROM if the address is within the range of the on-chip ROM/OTPROM/EPROM; otherwise the access is off-chip. The value of EA# is latched at reset. For devices without on-chip ROM/OTPROM/EPROM, EA# must be strapped to ground. PCA External Clock Input. External clock input to the 16-bit PCA timer. External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are set by a low level on INT1:0#. Programming Pulse. The programming pulse is applied to this pin for programming the on-chip OTPROM. Port 0. This is an 8-bit, open-drain, bidirectional I/O port. Port 1. This is an 8-bit, bidirectional I/O port with internal pullups. P1.2 P3.3:2 ECI INT1:0# I I PROG# P0.7:0 P1.0 P1.1 P1.2 P1.7:3 I I/O I/O ALE AD7:0 T2 T2EX ECI CEX3:0 CEX4/A17/ WAIT#/ WCLK A15:8 P2.7:0 I/O Port 2. This is an 8-bit, bidirectional I/O port with internal pullups. The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for pagemode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0). 10 PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 6. Signal Descriptions (Continued) Signal Name P3.0 P3.1 P3.3:2 P3.5:4 P3.6 P3.7 PSEN# Type I/O Description Port 3. This is an 8-bit, bidirectional I/O port with internal pullups. Alternate Function RXD TXD INT1:0# T1:0 WR# RD#/A16 -- O Program Store Enable. Read signal output. This output is asserted for a memory address range that depends on bits RD0 and RD1 in configuration byte UCONFIG0 (see RD# and Chapter 4, "Device Configuration," in the 8XC251SA/SB/SP/SQ Embedded Microcontroller User's Manual). Read or 17th Address Bit (A16). Read signal output to external data memory or 17th external address bit (A16), depending on the values of bits RD0 and RD1 in configuration byte UCONFIG0. (See PSEN# and Chapter 4, "Device Configuration," in the 8XC251SA/SB/SP/SQ Embedded Microcontroller User's Manual). Reset. Reset input to the chip. Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The port pins are driven to their reset conditions when a voltage greater than VIH1 is applied, whether or not the oscillator is running. This pin has an internal pulldown resistor, which allows the device to be reset by connecting a capacitor between this pin and VCC. Asserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation. Receive Serial Data. RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2, and 3. Timer 1:0 External Clock Inputs. When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count. Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal is the external clock input. For the clock-out mode, it is the timer 2 clock output. Timer 2 External Input. In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In auto-reload mode, a falling edge causes the timer 2 registers to be reloaded. In the up-down counter mode, this signal determines the count direction: 1 = up, 0 = down. Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0 and transmits serial data in serial I/O modes 1, 2, and 3. Supply Voltage. Connect this pin to the +5V supply voltage. Secondary Supply Voltage 2. This supply voltage connection is provided to reduce power supply noise. Connection of this pin to the +5V supply voltage is recommended. However, when using the 8XC251SB as a pin-for-pin replacement for the 8XC51FX, VSS2 can be unconnected without loss of compatibility. (Not available on DIP) RD# O P3.7/A16 RST I -- RXD T1:0 T2 I/O I I/O P3.0 P3.5:4 P1.0 T2EX I P1.1 TXD VCC VCC2 O PWR PWR P3.1 -- -- The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for pagemode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0). PRELIMINARY 11 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 6. Signal Descriptions (Continued) Signal Name VPP VSS VSS1 Type I GND GND Description Programming Supply Voltage. The programming supply voltage is applied to this pin for programming the on-chip OTPROM/EPROM. Circuit Ground. Connect this pin to ground. Secondary Ground. This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the 8XC251SA/SB/SP/SQ as a pin-for-pin replacement for the 8XC51BH, VSS1 can be unconnected without loss of compatibility. (Not available on DIP) Secondary Ground 2. This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the 8XC251SB as a pin-for-pin replacement for the 8XC51FX, VSS2 can be unconnected without loss of compatibility. (Not available on DIP) Real-time Wait State Input. The real-time WAIT# input is enabled by writing a logical `1' to the WCON.0 (RTWE) bit at S:A7H. During bus cycles, the external memory system can signal `system ready' to the microcontroller in real time by controlling the WAIT# input signal on the port 1.6 input. Wait Clock Output. The real-time WCLK output is driven at port 1.7 (WCLK) by writing a logical `1' to the WCON.1 (RTWCE) bit at S:A7H. When enabled, the WCLK output produces a square wave signal with a period of one-half the oscillator frequency. Write. Write signal output to external memory. Input to the On-chip, Inverting, Oscillator Amplifier. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal timing. Output of the On-chip, Inverting, Oscillator Amplifier. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected. Alternate Function EA# -- -- VSS2 GND -- WAIT# I P1.6/CEX3 WCLK O P1.7/CEX4/ A17 WR# XTAL1 O I P3.6 -- XTAL2 O -- The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for pagemode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0). 12 PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 7. Memory Signal Selections (RD1:0) RD1:0 00 01 10 P1.7/CEX/ A17/WCLK A17 P1.7/CEX4/ WCLK P1.7/CEX4/ WCLK P1.7/CEX4/ WCLK P3.7/RD#/A16 A16 A16 P3.7 only PSEN# Asserted for all addresses Asserted for all addresses Asserted for all addresses Asserted for 80:0000H WR# Asserted for writes to all memory locations Asserted for writes to all memory locations Asserted for writes to all memory locations Asserted only for writes to MCS 51 microcontroller data memory locations. Features 256-Kbyte external memory 128-Kbyte external memory 64-Kbyte external memory. One additional port pin. 64-Kbyte external memory. Compatible with MCS 51 microcontrollers. 11 RD# asserted for addresses 7F:FFFFH PRELIMINARY 13 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 4.0 ADDRESS MAP Table 8. 8XC251SA/SB/SP/SQ Address Map Internal Address) FF:FFFFH FF:4000H FF:3FFFH FF:0000H FE:FFFFH FE:0000H FD:FFFFH 02:0000H 01:FFFFH 01:0000H 00:FFFFH 00:E000H 00:DFFFH 00:0420H 00:041FH 00:0080H 00:007FH 00:0020H 00:001FH 00:0000H Description External Memory except the top eight bytes (FF:FFF8H-FF:FFFFH) which are reserved for the configuration array. External memory or on-chip nonvolatile memory (8Kbytes FF:0000H - FF:1FFFH, 16Kbytes FF:0000H - FF:3FFFH). External Memory Notes 1, 3, 10 3, 4, 5 3 Reserved 6 External Memory External memory or with configuration bit EMAP# = 0, addresses in this range access on-chip code memory in region FF: (16 Kbyte devices only). External Memory On-chip RAM (512 bytes 00:0020H - 00:021FH, 1024 bytes 00:0020H 00:041FH) On-chip RAM Storage for R0-R7 of Register File 3 5, 7 7 7 8 2, 9 NOTES: 1. 18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration). 2. The special function registers (SFRs) and the register file have separate internal address spaces. 3. Data in this area is accessible by indirect addressing only. 4. Devices reset into internal or external starting locations depending on the state of EA# and configuration byte information See EA#. See also UCONFIG1:0 bit definitions in the 8XC251SA/SB/SP/SQ Embedded Microcontroller User's Manual. 5. The 16-Kbyte ROM/OTPROM/EPROM devices allow internal locations FF:2000H-FF:3FFFH to map into region 00:. In this case, if EA# = 1, a data read to 00:E000H-00:FFFFH is redirected to internal ROM/OTPROM/EPROM (see bit 1 in UCONFIG0). This is not available for 8-Kbyte ROM/OTPROM/EPROM devices. 6. This reserved area returns indeterminate values. 7. Data is accessible by direct and indirect addressing. 8. Data is accessible by direct, indirect, and bit addressing. 9. Data is accessible by direct, indirect, and register addressing. 10. Eight addresses at the top of all external memory maps are reserved for current and future device configuration byte information. 14 PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 5.0 ELECTRICAL CHARACTERISTICS NOTICE: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. ABSOLUTE MAXIMUM RATINGS Storage Temperature ................................... -65C to +150C Voltage on EA#/VPP Pin to V SS ......................... 0 V to +13.0 V Voltage on Any other Pin to V SS ..................... -0.5 V to +6.5 V I OL per I/O Pin ................................................................. 15 mA Power Dissipation .......................................................... 1.5 W VSS ..................................................................................... 0 V WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. OperTA (Ambient Temperature Under Bias): Commercial ................................................. 0C to +70C ation beyond the "Operating Conditions" is not Express .................................................... -40C to +85C recommended and extended exposure beyond the "Operating Conditions" may affect device VCC (Digital Supply Voltage) .............................. 4.5 V to 5.5 V reliability. OPERATING CONDITIONS NOTE Maximum power dissipation is based on package heat-transfer limitations, not device power consumption. PRELIMINARY 15 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 5.1 D.C. Characteristics Parameter values apply to all devices unless otherwise indicated. Table 9. DC Characteristics at VCC = 4.5 - 5.5 V Symbol VIL VIL1 VIH VIH1 VOL Parameter Input Low Voltage (except EA#) Input Low Voltage (EA#) Input High Voltage (except XTAL1, RST) Input High Voltage (XTAL1, RST) Output Low Voltage (Port 1, 2, 3) Min -0.5 0 0.2VCC + 0.9 0.7VCC Typical Max 0.2VCC - 0.1 0.2VCC - 0.3 VCC + 0.5 VCC + 0.5 0.3 0.45 1.0 0.3 0.45 1.0 VCC - 0.3 VCC - 0.7 VCC - 1.5 Units V V V V V IOL = 100 A IOL = 1.6 mA IOL = 3.5 mA (Note 1, Note 2) IOL = 200 A IOL = 3.2 mA IOL = 7.0 mA (Note 1, Note 2) IOH = -10 A IOH = -30 A IOH = -60 A (Note 3) Test Conditions VOL1 Output Low Voltage (Port 0, ALE, PSEN#) V VOH Output High Voltage (Port 1, 2, 3, ALE, PSEN#) V NOTES: 1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: port 0 26 mA ports 1-3 15 mA Maximum Total IOL for all output pins 71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address lines are stabilizing. Typical values are obtained using VCC = 5.0, TA = 25C and are not guaranteed. 3. 4. 16 PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 9. DC Characteristics at VCC = 4.5 - 5.5 V (Continued) Symbol VOH1 Parameter Output High Voltage (Port 0 in External Address) Output High Voltage (Port 2 in External Address during Page Mode) Logical 0 Input Current (Port 1, 2, 3) Input Leakage Current (Port 0) Logical 1-to-0 Transition Current (Port 1, 2, 3) RST Pulldown Resistor Pin Capacitance Powerdown Current Idle Mode Current Operating Current 40 10 (Note 4) 10 (Note 4) 12 (Note 4) 45 (Note 4) 20 15 80 Min VCC - 0.3 VCC - 0.7 VCC - 1.5 V CC - 0.3 V CC - 0.7 V CC - 1.5 -50 +/-10 -650 Typical Max Units V Test Conditions IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA VIN = 0.45 V 0.45 < VIN < V CC VIN = 2.0 V VOH2 V IIL ILI ITL A A A RRST CIO IPD IDL ICC 225 k pF A mA mA FOSC = 16 MHz FOSC = 16 MHz FOSC = 16 MHz TA = 25 C NOTES: 1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: port 0 26 mA ports 1-3 15 mA Maximum Total IOL for all output pins 71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address lines are stabilizing. Typical values are obtained using VCC = 5.0, TA = 25C and are not guaranteed. 3. 4. PRELIMINARY 17 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER VCC VCC P0 RST 8XC251SA 8XC251SB 8XC251SP 8XC251SQ (NC) XTAL2 XTAL1 VSS EA# IPD VCC All other 8XC251SA/SB/SP/SQ pins are unconnected. A4208-01 Figure 5. IPD Test Condition, Powerdown Mode, VCC = 2.0 - 5.5V 70 60 50 ICC (mA) 40 30 20 10 ma x ive Act de mo (mA ) Act i od ve m e (m A) typ max Idle mod e (mA) typ Idle mode (mA) 9 10 11 12 13 14 15 16 0 1 2 3 4 5 6 7 8 Frequency at XTAL (MHz) A4400-01 Figure 6. ICC vs. Frequency (Mhz) 18 PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 5.2 Definition of AC Symbols Table 10. AC Timing Symbol Definitions Signals A D L Q R W Address Data In ALE Data Out RD#/PSEN# WR# H L V X Z Conditions High Low Valid No Longer Valid Floating 5.3 A.C. Characteristics Test Conditions: Capacitive load on all pins = 50 pF. Table 11 lists AC timing parameters for the 8XC251SA/SB/SP/SQ with no wait states. External wait states can be added by extending PSEN#/RD#/WR# and/or by extending ALE. In the table, Notes 3 and 5 mark parameters affected by an ALE wait state, and Notes 4 and 5 mark parameters affected by a PSEN#/RD#/WR# wait state. Figures 8-10 show the bus cycles with the timing parameters. Table 11. AC Characteristics Symbol FOSC TOSC Parameter XTAL1 Frequency 1/FOSC @ 12 MHz @ 16 MHz TLHLL ALE Pulse Width @ 12 MHz @ 16 MHz Address Valid to ALE Low @ 12 MHz @ 16 MHz Address Hold after ALE Low @ 12 MHz @ 16 MHz 73.3 52.5 58.3 37.5 15 15 @ Max Fosc (1) Min N/A N/A Max N/A N/A 83.3 62.5 (1+2M) TOSC - 10 (1+2M) TOSC - 25 ns (3) ns (3) ns 15 Fosc Variable Min 0 Max 16 Units MHz ns TAVLL TLLAX NOTES: 1. 16 MHz. 2. Specifications for PSEN# are identical to those for RD#. 3. In the formula, M=Number of wait states (0 or 1) for ALE. 4. In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#. 5. "Typical" specifications are untested and not guaranteed. PRELIMINARY 19 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 11. AC Characteristics (Continued) Symbol TRLRH (2) Parameter RD# or PSEN# Pulse Width @ 12 MHz @ 16 MHz WR# Pulse Width @ 12 MHz @ 16 MHz ALE Low to RD# or PSEN# Low @ 12 MHz @ 16 MHz ALE High to Address Hold @ 12 MHz @ 16 MHz @ Max Fosc (1) Min 146.6 105 146.6 105 58.3 37.5 83.3 62.5 106.6 65 0 Typ.=0 2 (5) Typ.=2 18 5 10 Typ.=2 5 (5) 156.6 115 10 10 156.6 115 171.6 130 0 Typ. = 0 (5) Typ.=25 Typ.=25 (5) 2 Max Fosc Variable Min 2(1+N) TOSC - 20 2(1+N) TOSC - 20 Max Units ns (4) ns (4) ns TOSC - 25 (1+2M)TOSC ns (3) ns (4) ns ns ns 18 10 TWLWH TLLRL (2) TLHAX TRLDV (2) RD#/PSEN# Low to valid Data/Instruction In @ 12 MHz @ 16 MHz TRHDX (2) Data/Instruction Hold Time. Occurs after RD#/PSEN# are exerted to VOH TRLAZ (2) TRHDZ1 RD#/PSEN# Low to Address Float Instruction Float after RD#/PSEN# High commercial @ 12 MHz and 16 MHz express @ 12 MHz and 16 MHz 2(1+N) Tosc - 60 TRHDZ2 Data Float after RD#/PSEN# High @ 12 MHz @ 16 MHz RD#/PSEN# High to ALE High (Instruction) @ 12 MHz @ 16 MHz RD#/PSEN# High to ALE High (Data) @ 12 MHz @ 16 MHz WR# High to ALE High @ 12 MHz @ 16 MHz ns 2Tosc - 10 ns 10 ns 2Tosc - 10 ns 2Tosc + 5 TRHLH1 TRHLH2 TWHLH NOTES: 1. 16 MHz. 2. Specifications for PSEN# are identical to those for RD#. 3. In the formula, M=Number of wait states (0 or 1) for ALE. 4. In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#. 5. "Typical" specifications are untested and not guaranteed. 20 PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 11. AC Characteristics (Continued) Symbol TAVDV1 Parameter Address (P0) Valid to Valid Data/Instruction In @ 12 MHz @ 16 MHz Address (P2) Valid to Valid Data/Instruction In @ 12 MHz @ 16 MHz Address (P0) Valid to Valid Instruction In @ 12 MHz @ 16 MHz Address Valid to RD#/PSEN# Low @ 12 MHz @ 16 MHz Address (P0) Valid to WR# Low @ 12 MHz @ 16 MHz Address (P2) Valid to WR# Low @ 12 MHz @ 16 MHz Data Hold after WR# High @ 12 MHz @ 16 MHz Data Valid to WR# High @ 12 MHz @ 16 MHz WR# High to Address Hold @ 12 MHz @ 16 MHz 121.6 80 126.6 85 146.6 105 63.3 42.5 138.6 97 156.6 115 @ Max Fosc (1) Min Max 243.2 160 268.2 185 116.6 75 2(1+M) TOSC - 45 2(1+M) TOSC - 40 2(1+M) TOSC - 20 TOSC - 20 ns (4) ns 2TOSC - 10 Fosc Variable Min Max 4(1+M/2) TOSC - 90 4(1+M/2) TOSC - 65 2TOSC - 50 ns (3) ns (3) ns (3) ns Units ns (3) ns (3) ns TAVDV2 TAVDV3 TAVRL (2) TAVWL1 TAVWL2 TWHQX TQVWH 2(1+N) TOSC - 28 TWHAX NOTES: 1. 16 MHz. 2. Specifications for PSEN# are identical to those for RD#. 3. In the formula, M=Number of wait states (0 or 1) for ALE. 4. In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#. 5. "Typical" specifications are untested and not guaranteed. PRELIMINARY 21 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 5.3.1 EXTERNAL BUS CYCLES, NONPAGE MODE TOSC XTAL1 ALE TLHLL TLLRL TRLRH TRHLH1 RD#/PSEN# TRLDV TRLAZ TLHAX TAVLL P0 TLLAX TRHDZ1 TRHDX D7:0 Instruction In A7:0 TAVRL TAVDV1 TAVDV2 P2/A16/A17 A15:8/A16/A17 The value of this parameter depends on wait states. See the table of AC characteristics. A4211-03 Figure 7. External Bus Cycle: Code Fetch (Nonpage Mode) 22 PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER TOSC XTAL1 ALE TLHLL TRLRH TLLRL TRHLH2 RD#/PSEN# TRLDV TRLAZ TLHAX TAVLL P0 TRHDZ2 TLLAX TRHDX D7:0 Data In A7:0 TAVRL TAVDV1 TAVDV2 P2/A16/A17 A15:8/A16/A17 The value of this parameter depends on wait states. See the table of AC characteristics. A4210-03 Figure 8. External Bus Cycle: Data Read (Nonpage Mode) PRELIMINARY 23 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER TOSC XTAL1 ALE TLHLL TWLWH TWHLH WR# TLHAX TAVLL TLLAX P0 A7:0 TAVWL1 TAVWL2 A15:8/A16/A17 TQVWH TWHQX D7:0 Data Out TWHAX P2/A16/A17 The value of this parameter depends on wait states. See the table of AC characteristics. A4179-01 Figure 9. External Bus Cycle: Data Write (Nonpage Mode) 24 PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 5.3.2 EXTERNAL BUS CYCLES, PAGE MODE TOSC XTAL1 ALE TLHLL TLLRL RD#/PSEN# TRLDV TRLAZ TLHAX TAVLL P2 TLLAX D7:0 Instruction In TAVDV3 A7:0/A16/A17 Page Hit TRHDZ1 TRHDX D7:0 Instruction In A15:8 TAVRL TAVDV1 TAVDV2 P0/A16/A17 A7:0/A16/A17 Page Miss The value of this parameter depends on wait states. See the table of AC characteristics. A page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle. A4213-02 state (2TOSC); a page miss requires two states (4TOSC). Figure 10. External Bus Cycle: Code Fetch (Page Mode) PRELIMINARY 25 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER TOSC XTAL1 ALE TLHLL TLLRL TRLRH TRHLH2 RD#/PSEN# TRLDV TRLAZ TLHAX TAVLL P2 TRHDZ2 TLLAX TRHDX D7:0 Data In A15:8 TAVRL TAVDV1 TAVDV2 P0/A16/A17 A7:0/A16/A17 The value of this parameter depends on wait states. See the table of AC characteristics. A4212-03 Figure 11. External Bus Cycle: Data Read (Page Mode) 26 PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER TOSC XTAL1 ALE TLHLL TWLWH TWHLH WR# TLHAX TAVLL TLLAX P2 A15:8 TAVWL1 TAVWL2 A7:0/A16/A17 TQVWH TWHQX D7:0 Data Out TWHAX P0/A16/A17 The value of this parameter depends on wait states. See the table of AC characteristics. A4182-01 Figure 12. External Bus Cycle: Data Write (Page Mode) PRELIMINARY 27 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 5.3.3 DEFINITION OF REAL-TIME WAIT SYMBOLS Table 12. Real-time Wait Timing Symbol Definitions Signals A D C Y W R Address Data WCLK WAIT# WR# RD#/PSEN# L X V Conditions Low Hold Setup 5.3.4 EXTERNAL BUS CYCLES, REAL-TIME WAIT STATES State 1 WCLK State 2 State 3 State 1 (next cycle) ALE TCLYV RD#/PSEN# TRLYX max TRLYX min TRLYV WAIT# P0 P2 TCLYX min TCLYX max RD#/PSEN# stretched A0-A7 D0-D7 A8-A15 stretched stretched A0-A7 A8-A15 A5000-01 Figure 13. External Bus Cycle: Code Fetch/Data Read (Nonpage Mode) 28 PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER State 1 WCLK State 2 State 3 State 4 TCLYX min ALE TCLYV WR# TWLYX max TWLYX min TWLYV WAIT# P0 P2 WR# stretched TCLYX max A0-A7 A8-A15 D0-D7 stretched stretched A5002-01 Figure 14. External Bus Cycle: Data Write (Nonpage Mode) State 1 WCLK State 2 State 3 State 1 (next cycle) ALE TCLYV RD#/PSEN# TRLYX max TRLYX min TRLYV WAIT# P2 P0 TCLYX min TCLYX max RD#/PSEN# stretched A8-A15 D0-D7 A0-A7 stretched stretched A8-A15 A0-A7 A5001-01 Figure 15. External Bus Cycle: Code Fetch/Data Read (Page Mode) PRELIMINARY 29 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER State 1 WCLK State 2 State 3 State 4 TCLYX min ALE TCLYV WR# TWLYX max TWLYX min TWLYV WAIT# P2 P0 WR# stretched TCLYX max A8-A15 A0-A7 D0-D7 stretched stretched A5003-01 Figure 16. External Bus Cycle: Data Write (Page Mode) Table 13. Real-time Wait AC Timing Symbol TCLYV TCLYX TRLYV TRLYX TWLYV TWLYX Parameter Wait Clock Low to Wait Set-up Wait Hold after Wait Clock Low PSEN#/RD# Low to Wait Set-up Wait Hold after PSEN#/RD# Low WR# Low to Wait Set-up Wait Hold after WR# Low Min 0 (2W)TOSC + 5 0 (2W)TOSC + 5 0 (2W)TOSC + 5 Max TOSC - 20 (1+2W)TOSC - 20 TOSC - 20 (1+2W)TOSC - 20 TOSC - 20 (1+2W)TOSC - 20 Units ns ns ns ns ns ns 30 PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 5.4 AC Characteristics -- Serial Port, Shift Register Mode Table 14. Serial Port Timing -- Shift Register Mode Parameter Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data hold after Clock Rising Edge Input Data Hold after Clock Rising Edge Clock Rising Edge to Input Data Valid Min 12TOSC 10TOSC - 133 2TOSC - 117 0 10TOSC - 133 Max Units ns ns ns ns ns Symbol TXLXL TQVSH TXHQX TXHDX TXHDV TXLXL TXD TXHQX TQVXH Set TI 2 3 4 5 6 7 RXD (Out) 0 1 TXHDV TAV TXHDX Valid Valid Valid Valid Valid Valid Set RI Valid RXD (In) Valid TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit. A2592-02 Figure 17. Serial Port Waveform -- Shift Register Mode 5.5 External Clock Drive Table 15. External Clock Drive Symbol 1/TCLCL TCHCX TCLCX TCLCH TCHCL Parameter Oscillator Frequency (F OSC) High Time Low Time Rise Time Fall Time 20 20 10 10 Min Max 16 Units MHz ns ns ns ns PRELIMINARY 31 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER TCLCH VCC - 0.5 0.7 VCC TCHCX TCLCX 0.45 V 0.2 VCC - 0.1 TCHCL TCLCL A4119-01 Figure 18. External Clock Drive Waveforms Inputs VCC - 0.5 0.45 V Outputs 0.2 VCC + 0.9 0.2 VCC - 0.1 VIH MIN VOL MAX AC inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45 V for a logic 0. Timing measurements are made at a min of VIH for a logic 1 and VOL for a logic 0. A4118-01 Figure 19. AC Testing Input, Output Waveforms VLOAD + 0.1 V VLOAD VLOAD - 0.1 V Timing Reference Points VOH - 0.1 V VOL + 0.1 V For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with IOL/IOH = 20 mA. A4117-01 Figure 20. Float Waveforms 32 PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 6.0 THERMAL CHARACTERISTICS Table 16. Thermal Characteristics Package Type 44-pin PLCC 40-pin PDIP 40-pin Ceramic DIP JA 46C/W 45C/W 30.5C/W JC 16C/W 16C/W 10C/W All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values change depending on operating conditions and application requirements. The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology. 7.0 NONVOLATILE MEMORY PROGRAMMING AND VERIFICATION CHARACTERISTICS Definition of Nonvolatile Memory Symbols Table 17. Nonvolatile Memory Timing Symbol Definitions 7.1 Signals A D Q S G E Address Data In Data Out Supply PROG# Enable H L V X Z Conditions High Low Valid No Longer Valid Floating 33 PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 7.2 Programming and Verification Timing for Nonvolatile Memory Programming Cycle P1, P3 Address (16 Bits) Verification Cycle Address TAVQV P2 Data In (8 Bits) TDVGL TAVGL TGHGL TGHDX TGHAX Data Out PROG# TGLGH TSHGL EA#/VPP 12.75V 5V TELQV TEHSH P0 Mode (8 Bits) Mode A4128-01 1 2 3 4 5 TGHSL TEHQZ Figure 21. Timing for Programming and Verification of Nonvolatile Memory Table 18. Nonvolatile Memory Programming and Verification Characteristics at TA = 21 - 27 C, VCC = 5 V, and VSS = 0 V Symbol VPP IPP FOSC TAVGL TGHAX TDVGL TGHDX TEHSH TSHGL TGHSL TGLGH Definition Programming Supply Voltage Programming Supply Current Oscillator Frequency Address Setup to PROG# Low Address Hold after PROG# Data Setup to PROG# Low Data Hold after PROG# ENABLE High to VPP VPP Setup to PROG# Low VPP Hold after PROG# PROG# Width 4.0 48TOSC 48TOSC 48TOSC 48TOSC 48TOSC 10 10 90 110 s s s Min 12.5 Max 13.5 75 6.0 Units D.C. Volts mA MHz 34 PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 18. Nonvolatile Memory Programming and Verification Characteristics at TA = 21 - 27 C, VCC = 5 V, and VSS = 0 V(Continued) TAVQV TELQV TEHQZ TGHGL Address to Data Valid ENABLE Low to Data Valid Data Float after ENABLE PROG# High to PROG# Low 0 10 48TOSC 48TOSC 48TOSC s 8.0 ERRATA 8. 9. 10. There are no known errata for this product. 9.0 REVISION HISTORY This (-003) revision of the 8XC251SA/SB/SP/SQ datasheet contains information on products with "[M] [C] '94 '95 C" as the last line of the topside marking. This datasheet replaces earlier product information. The following changes appear in the 003 datasheet: 1. 2. Real-time wait state operation is described in the datasheet. Memory map reserved locations are newly defined and the Memory Map is now referred to as the "Address Map." AC Characteristics have been updated. The following AC parameters have changed: TLLAX, TRLRH, TWLWH, TLLRL, TRLDV, TRHDZ1, TRHDZ2, TRHLH2, TWHLH, TAVDV1, TAVDV2, TAVRL, TAVWL1, TAVWL2, TQVWH, and TWHAX. DC Characteristics have been updated. The following DC specs have changed: IPD max, IDL typical, IDL max, I CC typical, and I CC max. An I CC vs. Frequency graph is included. Process information is no longer contained in the datasheet. The section "Programming and Verifying Nonvolatile Memory" has been deleted. See the 8XC251SA/SB/SP/SQ Embedded Microcontroller User's Manual. Timing and Characteristics for Programming and Verifying Nonvolatile 11. 12. 13. memory have been retained in this datasheet. Signature Byte information has been deleted. See the 8XC251SA/SB/SP/SQ Embedded Microcontroller User's Manual. Sections in the datasheet are numbered. New sections have been created to provide better organization. These include "Nomenclature," "Pinout," "Signals," "Address Map," "Electrical Characteristics," "Thermal Characteristics," "Nonvolatile Memory Programming and Verification Characteristics", "Errata," and "Revision History" Proliferation Options and Package Options are in the Nomenclature section. Temperature range is contained in the Electrical Characteristics section under "Operating Conditions" Bus timing diagrams have been organized into subsections. 3. 4. 5. 6. 7. The (-002) revision of the 8XC251SA/SB/SP/SQ datasheet contains information on products with "[M] [C] '94 '95 B" as the last line of the topside marking. This datasheet replaces earlier product information. The following changes appear in the 002 datasheet: 1. 2. 3. A corrected PDIP diagram appears on page 7. A corrected formula to calculate TLHLL is described on page 17. The RD#/PSEN# waveform is changed in Figure 11 on page 25. PRELIMINARY 35 |
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